[SHORTCUT] A trip down memory lane with Samsung

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[SHORTCUT] A trip down memory lane with Samsung

Samsung's first 5 nanometer chip released in November. [SCREEN CAPTURE]

Samsung's first 5 nanometer chip released in November. [SCREEN CAPTURE]



What is the Samsung Electronics chief strategy for the non-memory business?
 
Before jumping into the strategy, we need to make it clear what the non-memory business means. Often used by the Korean press and chipmakers, it is a chip business segment in which Samsung holds a relatively weak position compared to that in memory chips, like dynamic random access memory (DRAM) and NAND Flash.
 
Specifically, the term covers the production of the chips other than memory chips — such as central processing units for computers, application processors for smartphones and camera sensors. The area also includes foundry, or building chips by contract based on the designs from external customers.
 
Samsung is the largest manufacturer of memory chips, holding a 41.3 percent market share for DRAMs and 33.1 percent for NAND Flash, but its portion in foundry business is at 17.4 percent as of the third quarter — less than a third of the share held by Taiwan Semiconductor Manufacturing (TSMC).
 
To close the gap, Samsung pledged to pour 133 trillion won ($121 billion) into non-memory sector by 2030, with an aim of becoming the top player in the sector.
 
A large portion of the investment will go towards developing more advanced semiconductor manufacturing processes since the key for high-performance chips is to shrink the size of the process node used in chip fabrication.
 
Samsung and TSMC currently use 5-nanometer lithography processes as the two are the only chipmakers capable of employing the node size.
 
Both are poised to introduce 3-nanometer lithography in 2022.
 
 
What is the significance and impact of adopting 3-nanometer chips?
 
Samsung sees the transition as an opportunity to shake off its image of being a “secondary player” in terms of release speed and functionality.
 
So far, TSMC went several months or at least a quarter ahead in mass producing a new generation of chip based on smaller node sizes.
 
For instance, it began mass-producing 7-nanometer chips in the second quarter in 2018 while Samsung got there in the first quarter in 2019. The gap narrowed for 5-nanometer chips, with TSMC releasing them in large quantity in the first half of this year and Samsung in the third quarter.
 
For the planned 3-nanometer product, the gap will be further narrowed in since the two chipmakers appear to be targeting end-2022 as the time for mass-production.
 
TSMC went more specific to say the second half of 2022 while Samsung only mentioned the year.
 
The Korean tech company is also burdened to prove technical supremacy in the development of 3-nanometer chips because it plans to deploy a new transistor technology called Gate-All-Around FET ahead of TSMC.  
 
The technique is designed to enhance the transistor density of the chips and thus improve energy efficiency, as the new design allows for more expanded and flexible current flows across channels at transistor gate compared to the widely used finFET technique.
 
TSMC said it will use the technique for the 2-nanometer chips.
 
More generally, Samsung would also be able to cut the production cost in the long run with the micro-sized nodes because smaller process sizes reduce the space and electricity required for making chips while enhancing the computing power of the end product.
 
 
What does the nanometer size represent exactly?
 
Traditionally, the nanometer size refers to the distance between transistors on a chip. Transistor is considered as one of key components for semiconductor, switching or amplifying electrical signals. Depending on the type of chip produced, it sometimes indicates the width of the circuits through which electricity travels. The smaller the number, the more high-performing the chips are while consuming less energy.
 
Their size is also important because it could act as an indicator of transistor density since the number relates to the number of transistors that fit inside a specified space. For example, the transistor density of the chips currently produced using the 7-nanometer process is approximately between 130 and 230 million transistors per square millimeter.
 
 
What is the benefit of the 3-nanometer chip from the consumer perspective?
 
The introduction of the new generation chip is more about improving the processing speed and energy consumption of electronic devices than enabling new services that are hitherto nonexistent.  
 
The better performance could be experienced on electronic devices fitted with the 3-nanometer chip — including smartphones, tablets and laptops.  
 
Technically, the smaller node size could provide the end chip product in smaller sizes.
 
But those in the semiconductor industry said that the difference is not significant enough to be felt by consumers, since the chips currently in use are already miniscule.
 
BY PARK EUN-JEE   [park.eunjee@joongang.co.kr]
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