Samsung aims for 3 nanometer chips in early 2022

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Samsung aims for 3 nanometer chips in early 2022

Choi Si-young, president of Samsung’s foundry business, speaks during the Samsung Foundry Forum 2021, which was held online on Wednesday. [SAMSUNG ELECTRONICS]

Choi Si-young, president of Samsung’s foundry business, speaks during the Samsung Foundry Forum 2021, which was held online on Wednesday. [SAMSUNG ELECTRONICS]

 
Samsung Electronics is counting on revolutionary chipmaking technologies that drastically improve energy efficiency and data processing speeds as existing semiconductor architectures have reached their limits.  
 
The chipmaker announced Wednesday an aggressive roadmap toward more advanced chip manufacturing processes and how it will deploy a new transistor structure called Gate All Around (GAA) in its upcoming 3 nanometer lithography process.  
 
It will start adopting the GAA design in fabricating 3 nanometer chips in the first half of 2022, announced Choi Si-young, president of Samsung’s foundry business, during the annual Samsung Foundry Forum.
 
Given that Samsung has so far only mentioned the year 2022 as a starting point for the production of 3 nanometer chips, narrowing the schedule down to the first half suggests confidence in the progress made with the new chip fabrication process.  
 
Samsung said that the yield rate of its 3 nanometer chips is “approaching a similar level to the 4nm process,” which is currently in mass production.
 
This follows a June announcement that Samsung and U.S. partner Synopsys succeeded in testing the 3 nanometer process node using a design platform made by the U.S. unit.  
 
Samsung Electronics aims to produce 2 nanometer chips built on the GAA by 2025.  
 
Samsung’s 3 nanometer chips promise a 30 percent performance increase, a 50 percent power consumption reduction, and a 35 percent decline in area compared to 5 nanometer chips, according to a statement released by the company on Wednesday.  
 
“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continue technological innovation by application,” Choi said in the statement.  
"In the midst of further digitalization prompted by the Covid-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time," he said.  
 
Samsung hopes that advanced techniques will help it beat formidable competitors like TSMC and further ramp up production capacity amid a prolonged global shortage of chips.  
 
Samsung and TSMC currently use 5-nanometer lithography processes, the only two chipmakers capable of them.
 
If the roadmap is followed, the 3 nanometer chip could be the first chip category in which Samsung is ahead of TSMC in terms of release times.  
 
TSMC initially planned to enter volume production of 3 nanometer chips by the second half of 2022, but warned of several months of delays in a second quarter conference call.  
 
Another important distinction is that TSMC will begin to use the GAA technique for 2 nanometer chips instead of 3 nanometer ones.  
The GAA architecture is designed to enhance the transistor density of the chips and thus improve energy efficiency, as the new design allows for more expanded and flexible current flows across channels at transistor gates compared to the widely used finFET technique.
 
For the more distant future, the chipmaker is set to tap into a technology called neuromorphic engineering that aims to develop integrated circuits mimicking the human nervous system.  
 
Tech experts believe that by emulating the way neurons interact in the brain, chips could be able to perform more sophisticated tasks that require adaption and reasoning with far less energy consumption.  
 
Samsung Electronics and researchers from Harvard University presented a new approach for making neuromorphic chips last month in a paper entitled "Neuromorphic electronics based on copying and pasting the brain" published in Nature Electronics.  
 
The paper suggested a chip fabrication methodology in which the brain’s neuronal connection map is copied using a nanoelectrode array and the pasting of such a map onto a three-dimensional network of solid-state memories.  
 
Still, the approach is theoretical.  
 
“The vision we present is highly ambitious,” said Dr. Ham Don-hee, a fellow at the Samsung Advanced Institute of Technology (SAIT) and Professor of Harvard University.
 
“But working toward such a heroic goal will push the boundaries of machine intelligence, neuroscience, and semiconductor technology.”
 
 
 

BY PARK EUN-JEE [park.eunjee@joongang.co.kr]
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