Samsung Electronics set to manufacture 3-nanometer chips

Tech

Published: 27 Jun. 2022, 18:26 Updated: 27 Jun. 2022, 19:21

Samsung Electronics set to manufacture 3-nanometer chips

Wafers manufactured with 3-nanometer technology by Samsung Electronics are on display at the company's factory in Pyeongtaek, Gyeonggi, after President Yoon Suk-yeol and U.S. President Joe Biden signed autographs on them. [JOINT PRESS CORPS]

Samsung Electronics will meet its first-half deadline for the manufacturing of 3-nanometer chips and will become the first company to make semiconductors hitting this benchmark.

It has been working through yield challenges in recent months as it pushes the envelope on fabrication techniques in order to win market share in the highly competitive custom-chip business.

"The plan to mass-produce 3-nanometer chips in the first half is going as planned," said a spokesperson for the chipmaker.

A formal announcement is imminent, according to Kyung Kye-hyun, chief of semiconductor business, and the spokesperson.

"An announcement will be made soon," Kyung told reporters last week.

The 3-nanometer chips promise a 30-percent performance increase, a 50-percent power consumption reduction and a 35-percent decline in area compared to 5-nanometer chips, according to a statement released by the company.

As the production of 3-nanometer chips is set to be confirmed, market attention has shifted to whether the chipmaker has achieved high enough yields for the chips to be commercially successful. Low yields mean that more inputs must be used to get the same number of working semiconductors, and a rate of about 50 percent in the early stages of production is seen as a minimum for the product to make sense from the business point of view.

Earlier reports said that Samsung Electronics had achieved yields of around 10 percent for 3-nanometer chips, though the 30-percent range has since been mentioned in the local press. Samsung Electronics declined to comment about the issues and does not normally disclose its chip yields.

In 4- and 5-nanometer chips, the company achieved disappointing yields, with some estimates placing their yields as lower than those for competing products from TSMC, the leader in custom chip manufacturing.

Samsung Electronics has also been having trouble with the performance of phones with the Exynos 2200, which uses 4-nanometer technology. Processing speeds of Galaxy S22s fitted with the chip are lower for iPhone 13s and even the preceding 12 series using TSMC’s 5-nanometer technology.

The Korean tech company is trying to get beyond its image of being a secondary player in the foundry business with the release of 3-nanometer chips ahead of others.

In making the chips, the manufacturer will deploy a new transistor technology called Gate-All-Around FET ahead of TSMC.

The technique is designed to enhance the transistor density of the chips and thus improve energy efficiency, as the new design allows for more expanded and flexible current flows across channels at transistor gates compared to the widely used finFET technique.

TSMC plans to put a 3-nanometer chip into volume production in the second half of this year, with the company warning of three to four months of delay during a conference call last year.

Samsung Electronics displayed prototype 3-nanometer wafers when President Yoon Suk-yeol and U.S. President Joe Biden visited its semiconductor manufacturing complex in Pyeongtaek, Gyeonggi, last month.

BY PARK EUN-JEE [park.eunjee@joongang.co.kr]